In a copending application by the present applicant, assigned to Motorola Inc. and identified as U.S. patent application Ser. No. 052,995, a shift register is disclosed and claimed which is capable of programmable shifts, that is; the register may be shifted on a single clock pulse input by a variable number of stage places in either direction under programmed control. The register is especially useful in implementing the Data Encryption Standard (DES) as set forth in "Federal Information Processing Standards Publication (FIPS PUB) 46", Jan. 15, 1977, National Bureau of Standards. The specific capability of the disclosed shift register allowing single or double shifts in either left or right direction allows a very high speed 16 step implementation of the FIPS PUB 46 algorithm.
It is useful in systems, such as the DES system, to perform a parity check on the variable key to ensure reliable operation. While the most straight forward approach to parity checking would be to perform the checking function before the first step of the DES algorithm, this procedure does not assure the reliability of the key during algorithm operation. The first alternative would be to check parity on-line, one eight bit byte at a time, since each byte contains parity data. But the key variable is 64 bits in length and a full parity check would comprise 8 operations; at least eight clock times. In a system such as described in the copending application, no sequence of eight consecutive single shifts is available for this purpose, but, rather, the shift sequence comprises two single, six double, one single, six double and one single shift (all either left or right), in that order.